GEM5, NVMain에 L3 Cache 추가

1. configs/common/Options.py 파일에 l3 cache option 추가

parser.add_option("--l3cache", action="store_true")

2. configs/common/Caches.py 파일에 l3 cache class 추가

class L3Cache(BaseCache):
    assoc = 16
    hit_latency = 20
    response_latency = 20
    mshrs = 512
    tgts_per_mshr = 20
    write_buffers = 256
#   tags = MALRU()
    tags = LRU()

3. configs/common/CacheConfig.py 에 L3Cache 및 l3_cache_class 정의

    if options.l2cache:
        # Provide a clock for the L2 and the L1-to-L2 bus here as they
        # are not connected using addTwoLevelCacheHierarchy. Use the
        # same clock as the CPUs, and set the L1-to-L2 bus width to 32
        # bytes (256 bits).
        system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
                                   size=options.l2_size,
                                   assoc=options.l2_assoc)

        system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
                                     width = 32)
        system.l2.cpu_side = system.tol2bus.master
        system.l2.mem_side = system.membus.slave

위와 같은 부분을 아래와 같이 수정한다.

    if options.l2cache and options.l3cache :
        system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
                                   size=options.l2_size,
                                   assoc=options.l2_assoc)
        system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
                                   size=options.l3_size,
                                   assoc=options.l3_assoc)

        system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
                                     width = 32)
        system.tol3bus = CoherentBus(clk_domain = system.cpu_clk_domain,
                                     width = 32)
        system.l2.cpu_side = system.tol2bus.master
        system.l2.mem_side = system.tol3bus.slave
        system.l3.cpu_side = system.tol3bus.master
        system.l3.mem_side = system.membus.slave

    elif options.l2cache:
        # Provide a clock for the L2 and the L1-to-L2 bus here as they
        # are not connected using addTwoLevelCacheHierarchy. Use the
        # same clock as the CPUs, and set the L1-to-L2 bus width to 32
        # bytes (256 bits).
        system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
                                   size=options.l2_size,
                                   assoc=options.l2_assoc)

        system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
                                     width = 32)
        system.l2.cpu_side = system.tol2bus.master
        system.l2.mem_side = system.membus.slave

 

또한 "if options.cpu_type == " 부분에서 원하는 ISA에서 l3cache를 추가해야한다,

X86 ISA를 사용하길 원하므로, 마지막 else 문을 아래와 같이 수정한다.

else:
        dcache_class, icache_class, l2_cache_class = \
            L1Cache, L1Cache, L2Cache

위와 같은 부분을 아래와 같이 수정한다.

 

else:
        dcache_class, icache_class, l2_cache_class, l3_cache_class = \
            L1Cache, L1Cache, L2Cache, L3Cache

 

실행하면 아래와 같은 .dot file을 확인할 수 있다.